{"id":661,"date":"2019-05-28T13:24:03","date_gmt":"2019-05-28T11:24:03","guid":{"rendered":"https:\/\/www.realtime-it.de\/?page_id=661"},"modified":"2021-11-08T13:42:59","modified_gmt":"2021-11-08T12:42:59","slug":"scheduling-configuration","status":"publish","type":"page","link":"https:\/\/www.realtime-it.de\/en\/index.php\/scheduling-configuration\/","title":{"rendered":"Scheduling & Configuration"},"content":{"rendered":"
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Modular Framework Architecture<\/h3>\n
\n\nTo automate the TSN configuration and verification processes, we offer a versatile and modular framework. We combine the strengths of object-oriented modeling and logic programing concepts. Adequate interfaces are implemented to hide the system complexity from framework end-users.\n\nWith a focus on the IEEE 802.1Qbv scheduling, a created graphical model is transformed into a network knowledge base in Prolog. The facts and inference rules are used to extract the required information to build and solve the scheduling constraints. Using verification queries on the knowledge base, desired infrastructural properties can be verified.\n\n<\/div><\/div>\n<\/div><\/div><\/div><\/div>
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Generating the Gate Control Lists<\/h3>\n
The final result of the synthesis procedure contains the valid offset values for each time-triggered IEEE 802.1Qbv stream if the solver does not find any conflicting constraints or the synthesis terminates (NP-complete problem). Having the offsets of streams of a feasible schedule, we generate the GCL entries and transfer them to the relevant network ports.<\/div><\/div>\n<\/div><\/div><\/div><\/div>
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DEMO<\/strong>: Interactive IEEE 802.1Qbv Schedule Visualizer<\/h3>\n
Time-triggered Schedule Constraints Must be Satisfied on the Links<\/h5>\n
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